The disclosed embodiments of the present invention relate to generating a bias current, and more particularly, to a bias circuit and a phase-locked loop circuit using the same.
Due to the advance of the integrated circuit fabrication technology, reduced minimum channel width and supply voltage improve speed, power and area consumption of a digital circuit. However, this trend toward higher level integration complicates the design of an analog supportive circuit, such as a ring-type phase-locked loop (PLL) circuit that is used to generate clocks in a high performance system.
One challenge to PLL design in advanced process is the inevitably large gain of voltage controlled oscillator (VCO). Taking a PLL circuit with GHz output frequency for example, the VCO gain as large as several GHz/Volt is usually needed to cover process and temperature variation. However, this large VCO gain brings several drawbacks in the PLL circuit. First, noise injected on the control voltage node is amplified by the large gain. Second, for a given loop bandwidth, a large stabilizing capacitor must be used in a high VCO gain design. Therefore, an innovative PLL circuit with low jitter and low VCO gain is highly demanded.